Contact Information
● Email: gargin.law@gmail.com | jiajil7@uci.edu
● LinkedIn: https://www.linkedin.com/in/jiajian-luo
● Phone: +1 (949)-923-9873
● Location: Irvine, CA.
Summary
Mechanical Engineering Ph.D. specializing in semiconductor thermal management, advanced packaging, and model-driven optimization. 5+ years across device-, package-, and system-level thermal/structural/CFD simulation (ANSYS Icepak/Fluent/Mechanical, COMSOL), cleanroom microfabrication, and experimental validation. Built physics-informed machine learning models and automation pipelines (Python/MATLAB/APDL) to accelerate design space exploration and dynamic controls, including over 100k FEM runs with deep CNNs (less than 0.40% RMSE) and closed-loop hotspot mitigation (up to ~50% peak reduction). Research collaborations with NVIDIA, Texas Instruments, and Samsung.
Roles of Interest
● Electronic Packaging/Thermal Engineer: 2.5D/3D thermal-mechanical co-analysis, reduced-order modeling, interface/TIM trade-offs, early architecture studies.
● Thermal Applications/Systems Engineer: Data-center/vehicle/Energy storage thermal modeling, method development, application notes, and customer-facing data packages.
● FEA Modeling/Machine Learning Engineer: FEM/CFD automation, surrogate models, verification & validation frameworks, DOE and sensitivity-driven design.
Qualifications
● Thermal/CFD & Multiphysics FEA: Thermal/electrical/structural multi-physic modeling; Device/package/system thermal analysis; 2.5D/3D integration; co-packaged optics; data-center-scale HVAC/CDU modeling.
● Electronic Cooling: Developed CMOS-compatible micro-TECs with up to 8 °C reduction at 400 W/cm² hotspots; Fabricated prototype to experimentally cool 2.87 °C at a 30×44 µm² hotspot. Broad understanding in heat sink, cold plate, microchannel, vapor chamber, heat pipe and TIM,
● Data Center Thermal Management: System-level thermal analysis for the HVAC components in data centers, including CRACs, CDUs, perforated tiles, plenums, racks, etc. Scripted and automated CFD simulations for machine-learning-assisted control using supervised/reinforcement learnings.
● Advanced Packaging R&D: Understanding of 2.5D/3D packaging, co-packaged optics (TSV, hyper bond, BGA, PCB, SoC, RDL, etc.). Proficient in thermal/stress and diffusion-coupled modeling for packages; optimization of process-induced gradients (e.g., intense pulse light soldering).
● Experimental Validation: Thermal characterization (IR thermography, RTD/thermocouples); electrical characterization (four-point-probe testing, oscilloscope, lock-in amplifier, multimeters); wafer-level setups; model-test correlation and error analysis.
● Automation & AI/ML: Python, MATLAB (Simulink), APDL/PyANSYS for batch FEM/CFD, DOE, surrogate modeling; trained 120 M-parameter CNN surrogates (less than 0.40% RMSE) and deployed backtracking control (around 50–50.6% peak-T reduction, ~1.6 s).
● CAD & Layout Designs: SolidWorks/AutoCAD for prototypes/fixtures; Simulation geometry with ANSYS SpaceClaim, ModelDesigner and Discovery; GDS-based MEMS layouts (Tanner L-Edit, K-Layout).
Tools & Methods
● Simulation: ANSYS Icepak/Fluent/Mechanical; COMSOL Multiphysics; Flotherm.
● Validation/Metrology: IR thermography, RTDs, thermocouples, profilometer, SEM; wafer-level probing.
● Automation: Python (NumPy/TensorFlow/PyTorch), MATLAB, ANSYS APDL/PyANSYS; batch DOE, report generation.
● Cleanroom: Photolithography, DRIE/RIE, e-beam evaporation, LPCVD, oxidation, ion implantation, lift-off, dicing, wire bonding.
● CAD: SolidWorks/AutoCAD; ANSYS SpaceClaim, ModelDesigner and Discovery; GDS-based layouts (Tanner L-Edit, K-Layout).
Project Highlights
Thermal Design of Photonics-Enabled GPU (NVIDIA Internship)
● Scope: Packaging thermal/structural FEA for 2.5D/3D GPU modules with co-packaged optics and HBMs; material/interface trade-offs (TIM, solder, stackups) and reduced-order models for early design.
● Deliverables：Built ANSYS Icepak/Mechanical models to compare thermoelectric, liquid, and TIM-based cooling under realistic constraints; Provided design feedback that improved thermal uniformity / reliability and informed chip–package–system decisions.
CMOS-Compatible In-Chip Thermoelectric Cooling (Texas Instruments Collaboration)
● Scope: CMOS-compatible micro-TEC design, wafer process development, and coupled thermal–electrical modeling for device-level hotspot mitigation.
● Deliverables: Achieved 8 °C reduction at 400 W/cm² (100×100 µm² hotspot) in modeling and demonstrated 2.87 °C measured cooling at a 30×44 µm² hotspot on prototypes; Validated COMSOL models vs. IR/RTD data with strong correlation; supported yield analysis and reliability considerations.
Intense Pulse Light (IPL) Soldering — Package Uniformity & Reliability (Samsung Collaboration)
● Scope: Thermal-structural-diffusion modeling of BGA/PCB/chiplet assemblies under IPL; sensitivity studies for pulse energy.
● Deliverables: Reduced package temperature non-uniformity by ~78.5%, informing manufacturability and reliability improvements.
AI-Driven Dynamic Thermal Management for Multi-Hotspot SoCs
● Scope: Surrogate modeling and control for time-varying workloads; automated dataset generation (over 100k FEM cases) and deep CNNs (around 120 M params).
● Deliverables: Achieved less than 0.40% RMSE coupled thermal-electrical prediction; implemented backtracking control with around 50–50.6% peak-T reduction and ~1.6 s runtime.
Data-Center Thermal Modeling & Controls
● Scope: Raised-floor CFD (CRACs, tiles, plenums, racks, CDUs) and ML-assisted control optimization for cooling performance.
● Deliverables: Automated Fluent workflows, predicted outcomes under dynamic workloads, and explored control optimization strategies for energy reduction while maintaining compliance.
Representative Metrics & Milestones
● SoC thermal control: 50–50.6% hotspot peak-T reduction; ~1.6 s response; CNN surrogate less than 0.40% RMSE over 100k FEM cases.
● Device-level cooling (TEC): Up to 8 °C reduction at 400 W/cm² (simulation/analysis); 2.87 °C measured at 30×44 µm² hotspot; verified with IR/RTD.
● Package process optimization: ~78.5% temperature uniformity improvement under IPL soldering scenarios; reliability informed.
Collaboration & Industry Engagement
● Interned in NVIDIA circuit research group with electric/photonic/VLSI engineers on photonic-enabled GPU modules with thermal/packaging designs.
● Collaborated with Texas Instruments on device-level active thermoelectric cooling for power electronics.
● Partnered with Samsung on soldering process with thermal/packaging/reliability optimization.
● Activities included regular reviews, cross-functional trade-studies, and early-stage guidelines for manufacturability and layout.
Publications
● Machine Learning-Assisted Thermoelectric Cooling for Multi-Hotspot Dynamic Thermal Management, Journal of Applied Physics, 2024. (link)
● Dynamic Thermal Management in SOI Transistors Using Holey Silicon-Based Thermoelectric Cooling, IEEE TED, 2024. (link)
● Thermal Management of SOI-Based Devices Using Holey Silicon-Based Lateral Thermoelectric Cooler, The ASME 2024 Heat Transfer Summer Conference, 2024. (link)
● Dynamic Thermal Management of Power Transistors using Holey Silicon-Based Thermoelectric Cooling,” 2022 21st IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (iTherm), 2022. (link)
● Analysis of Non-Fourier Heat Conduction with Suddenly Applied Surface Heat Flux, J. Thermophysics & Heat Transfer, 2020. (link)
Education
● Ph.D., Mechanical Engineering, University of California, Irvine (GPA 3.9/4.0).
● M.S., Mechanical Engineering, University of California, Irvine (GPA 3.9/4.0).
● B.Eng., Power Engineering, Wuhan University (GPA 3.2/4.0)
