Nov 14, 2024
Thesis Project: In-Chip Thermoelectric Cooling
For the past four years, my PhD research has been mostly about developing an advanced in-chip thermoelectric cooling (TEC) device. This has been a rollercoaster of a project with Texas Instruments, moving from theoretical design and modeling to cleanroom fabrication and now, experimental testing and characterization. Watching a tiny idea grow into something real has been absolutely mind-blowing.
The idea actually came from my former colleague, Dr. Zongqing Ren, in his paper “Thermal conductivity anisotropy in holey silicon nanostructures and its impact on thermoelectric cooling.” He introduced this material called holey silicon—basically, silicon with periodic vertical holes. These holes make the silicon special by lowering in-plane thermal conductivity without messing up the high Seebeck coefficient. And because it’s silicon-based, it’s super compatible with existing chip tech.
We started by designing a lateral TEC because it’s easier to integrate directly into existing chip architectures. It’s like having a cooling system built into the chip itself. Early simulations using FEM showed it could cool down a power transistor by 8°C even with a heat flux density of 400 W/cm². Not bad for a start, right?
The first two years were all about optimizing the design and figuring out how to make it work practically in power transistors. That part of the work got published in IEEE Transactions on Electron Devices (10.1109/TED.2024.3358788)—yay! After that, it was time to get our hands dirty and actually build the thing.
We tweaked the design for lab fabrication and testing, did another round of simulations, and came up with two designs: the S-type and R-type TECs. Then we translated those into a 5-inch photomask with 1μm resolution and over 3 million features (yes, 3 million!), ordered from Compugraphics Inc. in the UK.
This was where things got intense. Cleanroom fabrication involved over 13 steps like oxidation, multi-layer lithography, ebeam evaporation, lift-off, and wet/dry etching. Honestly, I lost count of how many times things failed—over 100, easily. I probably spent more than 300 hours in the cleanrooms at UCI and UCLA. Huge shoutout to my PI, Prof. Jaeho Lee, for being so supportive through it all, because let’s be real, the cleanroom costs alone were over $25,000. Add in photomasks, photoresist, SOI wafers… yeah, it wasn’t cheap.
By December 2023, we finally had our first successful fabrication! Since then, we’ve done six more rounds to tweak and improve the design. Getting the TEC to perform its best means dealing with things like contact resistance and minimizing Joule heating from wires and electrodes.
Once the TECs were out of the cleanroom, we did post-processing like annealing, wire bonding, and chip mounting, and set up experiments like electrical (RTD) measurements and IR thermography. The experiments are still ongoing, but so far, we’ve seen actual cooling in the heating components. Fingers crossed for even better results soon!
It’s been an exhausting but super rewarding journey. This project is definitely going to be the highlight of my PhD and something I’ll carry forward with me as I keep pushing for new innovations. Stay tuned for the final results—I can’t wait to share more updates!
Written by JJ on Nov 14, 2024