Nov 4, 2025

[PhD Dissertation] Development of In-Chip Thermoelectric Cooling

For the past four years, my PhD research has focused on developing an in-chip thermoelectric cooling (TEC) device—one that could address the rising thermal challenges inside modern semiconductor systems. This project, carried out in close collaboration with Texas Instruments, took me through everything from theoretical modeling to cleanroom fabrication and ultimately to experimental validation. Watching a concept evolve into a working device has been one of the most fulfilling journeys of my doctoral life.

Nowadays, semiconductor chips are getting more and more heat, especially with the rise of AI and high-performance computing. From the early days of Intel Pentium to today’s advanced GPUs, chip power density has skyrocketed—especially in compact 2.5D and 3D packaging where heat has nowhere to go. These local hotspots don’t just warm things up—they break things down, reduce reliability, and shorten lifespan.

We knew traditional cooling methods like fans, heat spreaders, or liquid loops weren’t enough—especially for localized thermal issues inside chips. We needed something smarter. That’s where integrated thermoelectric cooling (TEC) came in. TEC works by running current through two materials to pump heat away, using the Peltier effect. It’s quiet, solid-state, and most importantly, local.

To make it work inside a chip, we used holey silicon [reference] —a silicon layer full of vertical nanopores. These “holes” reduce thermal conductivity by scattering phonons, which enables excellent thermoelectric performance. Even better, holey silicon is CMOS-compatible, so we could imagine scaling this in real semiconductor fabs.

Following the material selection, I designed a lateral TEC—one that pulls heat sideways, migrating thermal energy away from a hotspot and toward existing cooling surfaces like heat sinks. This made it a natural fit for power transistors or stacked packaging. Here’s the idea in picture form:

Before building anything, we started with simulation. First, we ran steady-state simulations to validate our concept. We modeled a 100×100μm² transistor hotspot with 400W/cm² (40mW) power density. The TEC brought its temperature down from 47°C to 39°C consuming 36mW. Interestingly, turning the TEC off actually made things worse (55°C) due to trapped heat—highlighting the need for smart control.

With promising simulations in hand, we moved to experimental development. I fabricated the device at UCLA’s cleanroom using SOI wafers. The setup included a serpentine resistor layer (for local heating and sensing), a TEC electrode layer (for cooling), and a silicon etched layer (for holey silicon pattern). In the end, the fabrication process involved 13 major steps, including oxidation, three lithography, two metal deposition, and deep etching. The final chip had a resolution of ~1μm.

The fabrication was far from easy (but later became my shiniest story in my PhD). Achieving such a novel and complex device meant that each of the sequential steps had to be carefully optimized and coordinated — every single step can take hours to run! At this point, a single misstep could ruin several days of progress. Looking back, it is overwhelming to revisit all those technical challenges I’ve encountered, all under uncertain funding situation and the risk of my Ph.D. being terminated. Despite high pressure, I focused on what I could control: documenting every failure mode, refining each process parameters, seeking advice from cleanroom staff, and maintaining efficient communication with my collaborators. To stay on schedule, I even slept in my car at the UCLA parking lots and worked through the night (It’s not worth commuting for 2 hours between Irvine to LA). Eventually, all the effort paid off — the fabrication succeeded, and we were finally able to move forward to experimental validation.

In our lab (which is much cozier than the cleanroom), I then wire-bonded the device onto a chip carrier and mounted it into a vacuum test chamber. I used the RTD (resistance temperature detector) with the four-point probe method to characterize the temperature difference in both steady state and transient state. The results were exciting. We ran a series of experiments with increasing local heating, from ~27°C all the way up to 280°C. The cooling performance tracked beautifully with temperature: from 0.3°C at lower temps to a peak of 2.87°C cooling at 280°C. This confirmed that TEC performance improves with hotter hotspots—consistent with Peltier physics.

Finally, we ran a set of high-fidelity simulations to explore how far this technology could go. Shrinking the neck size of holey silicon to 20nm could push cooling to nearly 19°C. Improving the Seebeck coefficient or switching from wire bonding to interconnect could each add several degrees. Combining all these improvements, we’re looking at a future where adaptive, embedded TEC arrays could offer precise thermal regulation for chiplets, stacked memory, photonics, or AI processors.

In the end, this journey has shown me how materials science, electrical engineering, and chip packaging all intersect around one very practical question: how do we keep our chips from overheating? I’m grateful to my advisor Prof. Jaeho Lee and our collaborators at Texas Instruments—Archana Venugopal and Jingjing Chen—for their constant support.

Written by JJ on Nov 14, 2024